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sensors data sheet v 1.0, 2010-11 final tle5012 tle5012-e0318 tle5012- e0742 angle sensor gmr-based angular sensor for rotor-position sensing
edition 2010-11 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
tle5012 final data sheet 3 v 1.0, 2010-11 we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: sensors@infineon.com tle5012 gmr-based angular sensor revision history: 2010-11, v 1.0 previous version: - page major changes since last revision general correction of typing errors
tle5012 table of contents final data sheet 4 v 1.0, 2010-11 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.1 internal power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.2 oscillator and pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.3 sd-adcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.4 digital signal processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.5 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.6 safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.3 gmr parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.4 angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.5 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4.6 clock supply (clk timing definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.5 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.1 synchronous serial communication (ssc) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5.1.1 ssc timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.5.1.2 ssc data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.5.1.3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5.1.3.1 tle5012 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.5.1.4 communication examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.5.2 pulse-width modulation interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.5.3 hall switch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.5.4 incremental interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.6 test structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.6.1 adc test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.7 overvoltage comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7.1 internal supply voltage comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7.2 v dd overvoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7.3 gnd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.7.4 v dd - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table of contents
tle5012 table of contents final data sheet 5 v 1.0, 2010-11 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.2 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.3 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.4 packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
tle5012 list of figures final data sheet 6 v 1.0, 2010-11 figure 1 sensitive bridges of the gmr sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2 theoretical output of the gmr sensor bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 tle5012 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5 pro-sil tm logo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6 application circuit for tle5012 with ssc and pwm in terface (using internal clk). . . . . . . . . . . . 15 figure 7 application circuit for tle5012 with hs mode (using in ternal clk). . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8 application circuit for tle5012 with ssc interface and iif (using external clk) . . . . . . . . . . . . . 16 figure 9 application circuit for tle5012 with only pwm interf ace (using internal clk) . . . . . . . . . . . . . . . 17 figure 10 operating magnetic induction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11 offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12 tle5012 signal path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 13 delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14 external clk timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15 ssc configuration in sensor-slave mode with pu sh-pull outputs (high speed application). . . . . . . 27 figure 16 ssc configuration in sensor-slave mode and open drain (safe bus systems) . . . . . . . . . . . . . . . . 28 figure 17 ssc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18 ssc data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 19 ssc data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20 ssc bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21 fast crc polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22 typical example for a pwm signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 23 hall switch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 24 hs hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 25 incremental interface with step/direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 26 incremental interface protocol wi th symbolic illustration of spi interface . . . . . . . . . . . . . . . . . . . 56 figure 27 iif index coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 28 adc test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 29 ov comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 30 gnd - off comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 31 v dd - off comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 32 pg-dso-8 package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 33 position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 34 footprint of pg-dso-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 35 tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 list of figures
tle5012 list of tables final data sheet 7 v 1.0, 2010-11 table 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5 electrical parameters for 4.5v < v dd < 5.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6 electrical parameters for 3.0v < v dd < 3.6v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8 basic gmr parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9 angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11 clk timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12 pad characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13 ssc push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14 ssc open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 15 structure of the command word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16 structure of the safety word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17 bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 18 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19 ssc command to read the angle value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 20 ssc command to read angle speed and angle revolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21 ssc command to change interface mode2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22 pwm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 23 hall switch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 24 incremental interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25 adc test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 26 ssc command to enable adc test vect or check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 table 27 structure of write data for some different test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 28 test comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 29 package parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 list of tables
product type marking ordering code package tle5012 5012 sp000477068 pg-dso-8 tle5012-e0318 5012e03 sp000611246 pg-dso-8 TLE5012-E0742 5012e07 sp000611250 pg-dso-8 tle5012 final data sheet 8 v 1.0, 2010-11 1 product description 1.1 overview the tle5012 is a 360 angle sensor that detects the orientation of a magnetic field by measuring sine and cosine angle components with monolithic integrated giant magn eto resistance (igmr) elements. highly precise angle values are maintained at various temperatures throughout the device?s lifetime using an internal autocalibration algorithm. data communications are accomplished with a bi-directional synchronous serial (ssc)-interface that is se rial peripheral interface (spi)-compatible. the absolute angle value and other values are transmitted via ssc or via a pulse-width modulation (pwm) protocol. the sine and cosine raw values can also be read out. these raw signals are digitally processed internally to calculate the angle orientatio n of the magnetic field (magnet). the tle5012 is a precalibrated sensor. the calibration pa rameters are stored in laser fuses. at start-up, the values of the fuses are written into flip-flops, where these values can be changed by the application-specific parameters. the tle5012-e0318 and TLE5012-E0742 are es pecially configured in a hall-switch emulation mode for motors with three or seven pole pairs. online diagnostic functions are prov ided to ensure reliable operation.
tle5012 product description final data sheet 9 v 1.0, 2010-11 1.2 features ? gmr-based principle ? integrated magnetic field sensing for angle measurement ? fully calibrated 0 - 360 angle measurement with revolution counter and angle speed measurement ? two separate highly accurate single-bit sd-adcs ? 15-bit representation of absolute angle va lue on the output (resolution of 0.01) ? 16-bit representation of sine/ cosine values on the interface ? max. 1.0 angle error over lifetime and temperature with activated auto-calibration ? bi-directional ssc interface up to 8 mbit/s ? supports safety integrity level (sil) with diagnostic functions and status information ? interfaces: ssc, pwm, incremental inte rface (iif), hall-sw itch mode (hsm) ? 0.25-m cmos technology ? automotive qualified: -40c to 150c (junction temperature) ? esd > 4 kv (hbm) ? rohs-compliant (pb-free package) 1.3 typical applications the tle5012 gmr-based angular sensor is designed fo r angular position sensing in automotive applications, such as: ? electrical commutated motor (e.g. used in electric power steering (eps)) ? rotary switch ? steering angle ? general angular sensing
tle5012 functional description final data sheet 10 v 1.0, 2010-11 2 functional description 2.1 general the gmr sensor uses vertical integration. this means that the gmr-sensitive areas are integrated above the logic portion of the tle5012 device. these gmr elements change their resistance depending on the direction of the magnetic field. four individual gmr elements are connected to one wheatstone sensor bridge. these gmr elements sense one of two components of the applied magnetic field: ? x component, v x (cosine) or the ? y component, v y (sine) the advantage of a full-bridge structure is that the amplit ude of the gmr signal is doubled and temperature effects cancel out each other. figure 1 sensitive bridges of the gmr sensor note: in figure 1 , the arrows in the resistors represent the magn etic direction which is fixed in the reference layer. if the external magnetic field is parallel to the direction of the reference layer, the resistance is minimal. if they are anti-par allel, resistance is maximal. the output signal of each bridge is only unambiguous over 180 between two maxima. therefore two bridges are oriented orthogonally to each other to measure 360. with the trigonometric function arctan, the true 360 angle value can be calculated, based on the relationship of x and y signals. because only the relative values influence the result, the absolute magnitude of the two signals is of minor importance. therefore, it is possible to compensate for most external influences on the amplitudes. v dd gnd adc x + gmr resistors adc x -adc y +adc y - v x v y 0 n s 90
tle5012 functional description final data sheet 11 v 1.0, 2010-11 figure 2 theoretical output of the gmr sensor bridges v angle 90 180 270 360 0 v x (cos) y component (sin) v y (sin) v y v x x component (cos)
tle5012 functional description final data sheet 12 v 1.0, 2010-11 2.2 pin configuration figure 3 pin configuration (top view) 2.3 pin description table 1 pin description pin no. symbol in/out function 1 clk i external clock (selection of interface) 1) 1) connected to v dd --> incremental interface is used; connected to gnd--> interface in if_md is used; sampling within power-on time; interface change within operation via ssc if possible 2 sck i ssc clock 3 csq i ssc chip select 4data (data / iif_index / hs3) i/o interface data: ssc data; iif index; hall switch signal 3 2) 5ifa (iif_a / hs1 / pwm) o interface a: iif phase a; hall switch signal 1; pwm 2) 2) depends on external circuit of clk and if_md setting 6v dd - supply voltage 7gnd-ground 8ifb (iif_b / hs2) o interface b: iif phase b; hall switch signal 2 2) 12 34 5 6 7 8 center of sensitive area
tle5012 functional description final data sheet 13 v 1.0, 2010-11 2.4 block diagram figure 4 tle5012 block diagram 2.5 functional block description 2.5.1 internal power supply the internal stages of the tle5012 have different voltage regulators. ? gmr voltage regulator vrg ? analog voltage regulator vra ? digital voltage regulato r vrd (derived from vra) these regulators are directly connected to the supply voltage v dd . 2.5.2 oscillator and pll the internal frequency oscillator fe eds the phase-locked loop (pll). therefore the ex ternal clock (clk) can also be used. 2.5.3 sd-adcs the sd-adcs transform the analog gmr voltages and temperature voltage into the digital domain. vrg vra vrd tle 5012 osc pll v dd x gmr y gmr temp sd- adc sd- adc sd- adc digital signal processing unit ccu cordic fuses ssc interface incremental if pwm hsm clk csq sck data ifa ifb gnd
tle5012 functional description final data sheet 14 v 1.0, 2010-11 2.5.4 digital signal processing unit the digital signal processing unit (dspu) contains the: ? c apture c ompare u nit ( ccu ), which is used to generate the pwm signal ? co ordinate r otation di gital c omputer ( cordic ), which contains the trigonometric function for angle calculation ? fuses, which contain the calibration parameters 2.5.5 interfaces different interfaces can be selected: ? ssc interface ?pwm ? incremental interface ? hall switch mode 2.5.6 safety features the tle5012 offers a multiplicity of safety features to support safety integrity leve l (sil). sensors with this performance are identified by the following logo: figure 5 pro-sil tm logo safety features are: ? test vectors switchable to adc input ? inversion or combination of filter input streams ? data transmission check via 8-bit cyclic redundancy check (crc) ? self-test routines ? two independent active interfaces possible ? overvoltage and undervoltage detection disclaimer pro-sil? is a registered tradem ark of infineon technologies ag. the pro-sil? trademark designates infineon produ cts which contain sil supporting features. sil supporting features are intended to support the over all system design to reach the desired sil (according to iec61508) or a-sil (according to iso26262) level for the high effi ciency safety system. sil respectively a-sil cert ification for such a system has to be reached on system level by the system responsible at an accredite d certification authority. sil stands for safety integrity level (according to iec 61508) a-sil stands for automotive-safety integrity level (according to iso 26262)
tle5012 specifications final data sheet 15 v 1.0, 2010-11 3 specifications 3.1 application circuit the application circuits shown in figure 6 , figure 7 , figure 8 and figure 9 show the various communication possibilities of the tle5012. figure 6 application circuit for tle5012 with ssc and pwm interface (using internal clk) figure 6 shows a basic block diagram of the tle5012 with pwm interface. this in terface is selectable by connecting clk to gnd. in addition to the pwm, the ssc interface could be used. within the ssc interface, the pwm mode is selectable between push-pull and open drain. 100 n ifa (pwm) ifb gnd data csq sck clk v dd (3.0 ? 5.5v) *) 1 k ? ssc pwm *) recommended , e .g. 470 ? ifb could remain open or connected via 10 k ? resistor to gnd. 10 k ? x gmr y gmr sd- adc sd- adc digital signal processing unit vrg vra vrd ssc interface fuses cordic pll tle 5012 sd- adc incremental if pwm hsm osc temp ccu
tle5012 specifications final data sheet 16 v 1.0, 2010-11 figure 7 application circuit for tle5012 with hs mode (using internal clk) figure 7 shows a basic block-diagram of the tle5012 in the hall switch mode. this in terface is selectable by connecting clk to gnd and csq to v dd . in addition to the hsm, the ssc interface can be us ed by pulling csq to gnd. within the ssc interface, the hsm is selectable between push-pull and open drain. figure 8 application circuit for tle5012 with ssc interface and iif (using external clk) figure 8 shows a basic block diagram of an angle sensor syst em using a tle5012 and a microcontroller for rotor- positioning applications. the interface configuration dep icted is needed for high-speed applications such as electrical commutated motor drives. it is possible to connect the tle5012 to a microcontroller via the incremental interface, and for safety reas ons also via the ssc interface. 100 n ifa (hs 1) ifb (hs 2) gnd data (hs3) csq sck clk v dd (3.0 ? 5.5v) *) *) recommended , e .g . 2. 2 k ? *) *) x gmr y gmr sd- adc sd- adc digital signal processing unit vrg vra vrd ssc interface fuses cordic pll tle5012 sd- adc incr em ental if pwm hsm osc temp ccu 100 n ifa (iif_a) ifb (iif_b) gnd data csq sck clk ssc pll x gmr y gmr sd- adc sd- adc digital signal processing unit vrg vra vrd ssc interface fuses cordic pll v dd (3.0 ? 5.5v) tle5012 c sd- adc incremental if pwm hsm osc temp ccu ccu *) *) r ecomm ended , e .g. 470 ? **) connected to v dd for use of internal clk ***) c onnected to m icrocontroller for use of exter nal clk ***) **)
tle5012 specifications final data sheet 17 v 1.0, 2010-11 the tle5012 exxxx can be configured with pwm only ( figure 9 ). this is not possible with the standard tle5012 type. 1) figure 9 application circuit fo r tle5012 with only pwm interface (using internal clk) 1) for more information, please contact infineon 100 n ifa (pwm) ifb gnd data csq sck clk v dd (3.0 ? 5.5v) 10 k ? 1 k ? 10 k ? data and ifb could rem ain open or connected via 10 k ? resistor to gnd . x gmr y gmr sd- adc sd- adc digital signal processing unit vrg vra vrd ssc interface fuses cordic pll tle5012 sd- adc incr em ental if pw m hsm osc temp ccu
tle5012 specifications final data sheet 18 v 1.0, 2010-11 3.2 absolute maximum ratings attention: stresses above the max. values listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device. 3.3 operating range the following operating conditions must not be exceeded in order to ensure correct operation of the tle5012. all parameters specified in th e following sections refer to these opera ting conditions, unless otherwise noted. table 3 is valid for -40c < t j < 150c unless otherwise noted. table 2 absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. voltage on v dd pin with respect to ground (v ss ) v dd -0.5 - 6.5 v max. 40 h/lifetime voltage on any pin with respect to ground (v ss ) v in -0.5 - 6.5 v additionally v dd + 0.5 v may not be exceeded junction temperature t j -40 - 150 c - - 150 c for 1000 h not additive magnetic field induction b - - 125 mt max. 5 min @ t a = 25c -- 100 mt max. 5 h @ t a = 25c storage temperature t st -40 - 150 c without magnetic field table 3 operating range parameter symbol values unit note / test condition min. typ. max. supply voltage v dd 3.0 5.0 5.5 v 1) output current (data-pad) i q - - -25 ma pad_drv =?0x?, sink current 2)3) - - -5 ma pad_drv =?10?, sink current 2)3) - - -0.4 ma pad_drv =?11?, sink current 2)3) output current (ifa / ifb-pad) i q - - -15 ma pad_drv =?0x?, sink current 2)3) - - -5 ma pad_drv =?1x?, sink current 2)3) input voltage v in -0.3 - 5.5 v v dd + 0.3 v may not be exceeded
tle5012 specifications final data sheet 19 v 1.0, 2010-11 the field strength of a magnet can be selected within the colored area in figure 10 . by limitation of the junction temperature, a higher magnetic field can be applied. in case of a maximum temperature t j =100c a magnet with up to 60mt at t a =25c is allowed. figure 10 magnet performance (ambient temperature) note: the thermal resistances listed in table 29 ?package parameters? on page 61 must be used to calculate the corresponding ambient temperature. magnetic induction at t a = 25c 4)5) b xy 30 - 50 mt -40c < t j < 150c b xy 30 - 60 mt -40c < t j < 100c b xy 30 - 70 mt -40c < t j < 85c expanded magnetic induction at t a = 25c 4)5) b xy 25 - 30 mt additional angle error of 0.1 6) angle range ang 0 - 360 1) directly blocked with 100-nf ceramic capacitor 2) max. current to gnd over open-drain output 3) at v dd = 5v 4) values refer to an homogenous magnetic field (b xy ) without vertical magnetic induction (b z = 0mt) 5) see figure 10 6) 0 h table 3 operating range (cont?d) parameter symbol values unit note / test condition min. typ. max.
tle5012 specifications final data sheet 20 v 1.0, 2010-11 calculation of the junction temperature the total power dissipation p tot of the chip increases its temperature above the ambient temperature. the power multiplied by the total thermal resistance r thja (junction to ambient) leads to the final junction temperature. r thja is the sum of the addition of the values of the two components junction to case and case to ambient. (1) example (assuming no load on v out ): (2) for molded sensors, the calculation with r thjc is more appropriate. 3.4 characteristics 3.4.1 electrical parameters the indicated electrical parameters apply to the full op erating range, unless otherwise specified. the typical values correspond to a supply voltage v dd = 5.0 v and 25 c, unless individually specified. all other values correspond to -40 c < t j < 150c. table 4 electrical parameters parameter symbol values unit note / test condition min. typ. max. supply current i dd -1416ma por level v por 2.0 - 2.9 v power-on reset por hysteresis 1) 1) not subject to production test - ve rified by design/characterization v porhy -30- mv pull-up current i pu -10 - -225 a csq -10 - -150 a data pull-down current i pd 10 - 225 a sck 10 - 150 a clk, ifa, ifb power-on time t pon -57 msv dd > v ddmin 2) 2) within ?power-on time,? write access is not permitted ) ( out out dd dd thja tot thja a j thca thjc thja i v i v r p r t t t t r r r + = = + = + = (i dd , i out > 0, if direction is into ic) >@ >@ > @ k va a v w k t ma i v v dd dd 5 . 10 0 014 . 0 5 150 14 5 = + ? ? ? ? ? ? = = =
tle5012 specifications final data sheet 21 v 1.0, 2010-11 3.4.2 esd protection table 5 electrical parameters for 4.5v < v dd < 5.5v parameter symbol values unit note / test condition min. typ. max. input signal low level v l5 - - 0.3 v dd v input signal high level v h5 0.7 v dd -- v output signal low level v ol5 --1 vdata; i q = - 25 ma (pad_drv=?0x?), i q = - 5 ma (pad_drv=?10?), i q = - 0.4 ma (pad_drv=?11?) - - 1 v ifa,ifb; i q = - 15 ma (pad_drv=?0x?), i q = - 5 ma (pad_drv=?1x?) table 6 electrical parameters for 3.0v < v dd < 3.6v parameter symbol values unit note / test condition min. typ. max. input signal low level v l3 - - 0.2 v dd v input signal high level v h3 0.8 v dd -- v output signal low level v ol3 --0.9vdata; i q = - 15 ma (pad_drv=?0x?), i q = - 3 ma (pad_drv=?10?), i q = - 0.24 ma (pad_drv=?11?) - - 0.9 v ifa,ifb; i q = - 10 ma (pad_drv=?0x?), i q = - 3 ma (pad_drv=?1x?) table 7 esd protection parameter symbol values unit notes min. max. esd voltage v hbm - 4.0 kv human body model 1) 1) human body model (hbm) according to aec-q100-002 v sdm - 0.5 kv socketed device model 2) 2) socketed device model (sdm) acco rding to esda/ansi/esd sp5.3.2-2008
tle5012 specifications final data sheet 22 v 1.0, 2010-11 3.4.3 gmr parameters all parameters apply over b xy = 30mt and t a = 25c, unless otherwise specified. figure 11 offset and amplitude definition table 8 basic gmr parameters parameter symbol values unit note / test condition min. typ. max. x, y output range rg adc - - 23230 digits 4) x, y amplitude 1) 1) see figure 11 a x , a y 6000 9500 15781 digits 3922 - 20620 digits operating range x, y synchronism 2) 2) k = 100*(a x /a y ) k 87.5 100 112.49 % x, y offset 3) 3) o y =(y max + y min ) / 2; o x = (x max + x min ) / 2 o x , o y -2048 0 +2047 digits x, y orthogonality error -11.25 0 +11.24 x, y without field x 0 , y 0 -5000 - +5000 digits without magnet 4) 4) not subject to production test - ve rified by design/characterization angle 90 180 270 360 0 +a offset v y 0 -a
tle5012 specifications final data sheet 23 v 1.0, 2010-11 3.4.4 angle performance after internal calculation the sensor has a remaining error, as shown in table 11 . the error value refers to b z = 0mt and the operating conditions given in table 3 ?operating range? on page 18 . the overall angle error represents the relative angle erro r. this error describes the deviation from the reference line after zero angle definition. autocalibration the autocalibration enables online parameter calculation and therefore reduces the angle error due to temperature drift, lifetime drift, and misalignments. the tle5012 is a pre-calibrated sensor. after start-up, the parameters out of the laser fuses get loaded into flip- flops. the tle5012 needs more than a full revolution to generate new parameters. the update mode can be chosen within the interface mode 2 register (autocal). the parameters are updated in a smooth way to avoid an angle jump on the outpu t. therefore only one lsb will be change d within the choosen range or time. the autocalibration is done continuously. autocal modes: ? 00: no autocalibration ? 01: autocalibration mode 1. only one lsb to final values within the update time t upd (depending on fir_md setting). ? 10: autocalibration mode 2. only one lsb update over one full revolution. after update of one lsb, the autocalibration will calculat e the parameters again. ? 11: autocalibration mode 3. only one lsb to final values within an angle range of 11.25. 3.4.5 signal processing the signal path of the tle5012 is depicted in figure 12 . it consists of the gmr bridge, adc, filter, and angle calculation. depending on the filter configuration, various total delay ti mes are achieved. in addition to this delay time, the delay time of the interface has to be consider ed. the delay time leads to an additional angle error at higher speeds. by enabling the prediction , the signal delay time can be reduced ( figure 13 ). the prediction uses the difference between current and last angle value and ca lculates the output value by adding this difference to the current value. a linear prediction is thereby achieved. (3) table 9 angle performance parameter symbol values unit note / test condition min. typ. max. overall angle error (with auto- calibration) err -0.6 1) 1) at 25c, b = 30 mt 1.0 including lifetime and temperature drift 2)3)4) 2) including hysteresis error, caused by revolution direction change. 3) only with calibrated gmr-compensation parameters of custom er setup; relative error after zero angle definition. 4) not subject to production test - ve rified by design/characterization overall angle error (without auto- calibration) err -0.6 1) 1.6 including temperature drift 2)3)5) 5) 0 h ) 1 ( ) ( 2 ) 1 ( ? ? ? = + t t t d d d
tle5012 specifications final data sheet 24 v 1.0, 2010-11 figure 12 tle5012 signal path at fir_md = 0 only raw values can be read out, due to the more time consuming angle calculation. table 10 signal processing parameter symbol values unit note / test condition min. typ. max. update rate at interface t upd - 21.3 - s fir_md = 0 (only raw values) 1)2) 1) depends on internal oscillator frequency variation ( section 3.4.6 ) 2) not subject to production test - ve rified by design/characterization -42.7- sfir_md = 1 1)2) - 85.3 - s fir_md = 2 (default) 1)2) -170.6- sfir_md = 3 1)2) angle delay time 3) 3) valid at constant rotation speed t adel -6070 sfir_md = 1 1)2) -8095 sfir_md = 2 1)2) - 120 140 s fir_md = 3 1)2) angle delay time with prediction 3) t adel - 20 30 s fir_md = 1; predict = 1 1)2) - 5 20 s fir_md = 2; predict = 1 1)2) - -40 -20 s fir_md = 3; predict = 1 1)2) angle noise n angle - 0.11 - fir_md = 0, (1 sigma) 2) - 0.08 - fir_md = 1, (1 sigma) 2) - 0.05 - fir_md = 2, (1 sigma) 2) (default) - 0.04 - fir_md = 3, (1 sigma) 2) x gmr y gmr sd- adc sd- adc angle calculation filter filter tle5012 microcontroller if adel t delif t upd t
tle5012 specifications final data sheet 25 v 1.0, 2010-11 figure 13 delay of sensor output time angle with prediction without prediction t adel t upd magnetic field direction sensor output
tle5012 specifications final data sheet 26 v 1.0, 2010-11 3.4.6 clock supply (clk timing definition) if the external clock supply is selected, the clo ck signal input clk must fu lfill certain requirements: ? the high or low pulse width must not exceed the s pecified values, because the pll needs a minimum pulse width and must be spike filtered. ? the duty cycle factor should be 0.5 but ca n deviate to the values limited by t clkh(f_min) and t clkl(f_min) . ? the pll is triggered at the positive edge of the clock; if more than 2 edges are missing, a chip reset is generated automatically. figure 14 external clk timing definition table 11 clk timing specification parameter symbol values unit note / test condition min. typ. max. input frequency f clk 3.8 4.0 4.2 mhz clk duty cycle 1)2) 1) minimum duty cycle factor: t clkh(f_min) / t clk(f_min) with t clk(f_min) = 1 / f clk(f_min) 2) maximum duty cycle factor: t clkh(f_max) / t clk(f_min) with t clkh(f_max) = t clk(f_min) - t clkl(min) clk duty 30 50 70 % clk rise time t clkr - - 30 ns from v l to v h 3) 3) not subject to production test - ve rified by design/characterization clk fall time t clkf - - 30 ns from v h to v l 3) digital clock f dig 22.8 24 25.2 mhz internal oscillator frequency f clk 3.8 4.0 4.2 mhz t clkh t clkl t clk t v l v h
tle5012 specifications final data sheet 27 v 1.0, 2010-11 3.5 interfaces within the register mod_3, the driver strength and so the slope for push-pull communication can be varied with the sensor output. the driver strength is specified in table 3 and the slope fall and rise times in table 12 . 3.5.1 synchronous serial co mmunication ( ssc) interface the 3-pin ssc interface has a bi-dir ectional push-pull data line, serial cl ock signal, and chip select. the ssc interface is designed to communicate with a mi crocontroller peer-to-peer for fast applications. figure 15 ssc configuration in sensor-slave mode with push-pull outputs (high speed application) table 12 pad characteristics parameter symbol values unit note / test condition min. typ. max. output fall time t fall , t rise - - 8 ns data, 50 pf, pad_drv=?00? 1)2) 1) valid for push-pull output 2) not subject to production test - ve rified by design/characterization output rise time - - 28 ns data, 50 pf, pad_drv=?01? 1)2) - - 45 ns data, 50 pf, pad_drv=?10? 1)2) - - 130 ns data, 50pf, pad_drv=?11? 1)2) - - 15 ns ifa/ifb, 20 pf, pad_drv=?0x? 1)2) - - 30 ns ifa/ifb, 20 pf, pad_drv=?1x? 1)2) ssc communication for peer to peer data transmission between tle5012 and c shift reg. shift reg. clock gen. data mrst mtsr sck sck (ssc slave) tle 5012 c (ssc master) csq csq **) *) *) en en *) optional , e.g. 100 ? **) optional , e.g . 470 ?
tle5012 specifications final data sheet 28 v 1.0, 2010-11 another possibility is a 3-pin ssc interface with bidirecti onal open-drain data line, serial clock signal, and chip select. this setup is designed to co mmunicate with a microcontroller in a bus system, together with other ssc slaves (e.g. two tle5012 devices for redundancy reas ons). this mode can be activated using bit ssc_od. figure 16 ssc configuration in sensor-slave mode and open drain (safe bus systems) 3.5.1.1 ssc timing definition figure 17 ssc timing ssc inactive time (cs off ) the ssc inactive time defines the delay time after a transfer before the tle5012 can be selected again. table 13 ssc push-pull timing specification parameter symbol values unit note / test condition min. typ. max. ssc baud rate f ssc - 8.0 - mbit/s 1) csq setup time t css 105 - - ns 1) ssc communication for bus data transmission between one or more tle5012 and c shift reg. shift reg. clock gen. data sck sck (ssc slave) tle 5012 c (ssc master) csq csq *) *) *) *) typ. 1k ? *) optional , e.g . 100 ? mrst mtsr sck t css t sckp t sckh t csh csq t sckl t csoff t datas data t datah t sckoff
tle5012 specifications final data sheet 29 v 1.0, 2010-11 csq hold time t csh 105 - - ns 1) csq off t csoff 600 - - ns ssc inactive time 1) sck period t sckp 120 125 - ns 1) sck high t sckh 40 - - ns 1) sck low t sckl 30 - - ns 1) data setup time t datas 25 - - ns 1) data hold time t datah 40 - - ns 1) write read delay t wr_delay 130 - - ns 1) sck off t sckoff 170 - - ns 1) 1) not subject to production test - ve rified by design/characterization table 14 ssc open-drain timing specification parameter symbol values unit note / test condition min. typ. max. ssc baud rate f ssc - 2.0 - mbit/s pull-up resistor = 1k ? 1) 1) not subject to production test - ve rified by design/characterization csq setup time t css 300 - - ns 1) csq hold time t csh 400 - - ns 1) csq off t csoff 600 - - ns ssc inactive time 1) sck period t sckp 500 - - ns 1) sck high t sckh -190- ns 1) sck low t sckl -190- ns 1) data setup time t datas 25 - - ns 1) data hold time t datah 40 - - ns 1) write read delay t wr_delay 130 - - ns 1) sck off t sckoff 170 - - ns 1) table 13 ssc push-pull timing specification (cont?d) parameter symbol values unit note / test condition min. typ. max.
tle5012 specifications final data sheet 30 v 1.0, 2010-11 3.5.1.2 ssc data transfer the ssc data transfer is word-aligned. the following transfer words are possible: ? command word (to access and change operating modes of the tle5012) ? data words (any data transferred in any direction) ? safety word (confirms the data transfer and provide status information) figure 18 ssc data transfer (data-read example) figure 19 ssc data transfer (data-write example) command word the tle5012 is controlled by a command word. it is sent fi rst at the start of every data transmission. the structure of the command word is shown in table 15 , where the update (upd) bit allows access to current or updated values. if an update command is issued and upd is set, the immediate values are stored in the update buffer simultaneously. this enables a snapshot of all necessary sy stem parameters at the same time. bits with an update buffer are marked by an ?u? in the bit type in the register description. table 15 structure of the command word name bits description rw [15] read - write 0:write 1:read lock [14..11] 4-bit lock value 0000 b : default operating access for addresses 0x00:0x04 1010 b : config- access for addresses 0x05:0x11 upd [10] update register access 0: access to current values 1: access to updated values command read data 1 read data 2 safety-word ssc-master is driving data ssc-slave is driving dat a t wr_delay command write data 1 safety-word ssc-master is driving data ssc-slave is driving dat a t wr_delay
tle5012 specifications final data sheet 31 v 1.0, 2010-11 safety word the safety word contains following bits: bit types the types of bits used in the registers are listed here: addr [9..4] 6-bit address nd [3..0] 4-bit number of data words table 16 structure of the safety word name bits description stat chip and interface status [15] indication of chip rese t (resets after readout) via ssc 0: reset occurred 1: no reset reset: 1 b [14] system error (e.g. overvoltage; undervoltage; v dd -, gnd- off; rom;...) 0: error occurred (s_v r; s_dspu; s_ov; s_xyo l: s_magol; s_adcm; s_fuse) 1: no error [13] interface access error (access to wrong address; wrong lock) 0: error occurred 1: no error [12] valid angle value (no system error; no interface error; no_gmr_a = ?0?; no_gmr_xy=?0?) 0: angle value invalid 1: angle value valid resp [11..8] sensor number response indicator the sensor no. bit is pulled low and the other bits are high crc [7..0] cyclic redundancy check table 17 bit types abbreviation function description r read read-only registers w write read and write registers u update update buffer for this bit is present. if an update is issued and the update register access bit (upd in command wo rd) is set, the immediate values are stored in this update buffer simultaneously. this enables a snapshot of all necessary system parame ters at the same time. table 15 structure of the command word name bits description
tle5012 specifications final data sheet 32 v 1.0, 2010-11 data communication via ssc figure 20 ssc bit ordering (read example) the data communication via ssc interface has the following characteristics: ? the data transmission order is ?m ost significant bit (msb) first?. ? data is put on the data line with the rising edge on sck and read with the fa lling edge on sck. ? the ssc interface is word-aligned. all functions are activated after each transmitted word. ? a ?high? condition on the negated chip select pin (csq) of the selected tle5012 interrupts the transfer immediately. the crc calculat or is automatically reset. ? after changing the data direction, a delay (t wr_delay ) has to occur before continuing the data transfer. this is necessary for internal register access. ? every access to the tle5012 with the number of data (nd) 1 is performed with address auto-increment. at an overflow at address 3f h the transfer continuous at address 00 h . ? with nd = 0, no auto-increment is done and a continuous ly readout of the same address can occur. afterwards no safety word is sent and the transfer ends with high condition on csq. ? after every data transfer with nd 1, the 16-bit safety word will be appended by the selected tle5012. ? after the safety word is sent, the transfer ends. to st art another data transfer, the csq has to be deselected once for t csoff . ? the ssc is by default push-pull. the push-pull driver is active only if the tle5012 has to send data; otherwise the push-pull is disabled for receiving data from the microcontroller. cyclic redundancy check (crc) ? this crc complies with the j1850 bus specification. ? every new transfer rese ts the crc generation. ? every byte of a transfer will be taken into account to generate th e crc (also the sent command(s)). ? generator polynomial: x8+x4+x3+x2+1, but for the crc generation the fast crc generation circuit is used (see figure 21 ) ? the remainder of the fast crc ci rcuit is initial set to ?11111111 b ?. ? the remainder is inverted before transmission. figure 21 fast crc polynomial division circuit sck data 8 11 10 9 msb 14 13 12 csq ssc transfer lsb 321 7 6 5 4 command w ord data word (s) ssc -m aster is dr iving dat a ssc -slave is driving dat a lsb 1 rw addr length lock msb t wr_delay upd xor x7 x6 x5 x4 x3 x2 xor x0 xor xor input serial crc output & tx_crc 1111 1 1 1 1 x1 parallel remainder
tle5012 specifications final data sheet 33 v 1.0, 2010-11 3.5.1.3 registers this section describes the registers of the tle5012. it also specifies the read/write access rights of the specific registers. table 18 identifies the values with symbols. access to the registers is accomplished via the ssc interface. the register is addressed wordwise. table 18 registers overview register short name register long name offset address page number registers , tle5012 register stat status register 00 h 34 acstat activation status register 01 h 36 aval angle value register 02 h 37 aspd angle speed register 03 h 38 arev angle revolution register 04 h 39 fsync frame synchronization register 05 h 39 mod_1 interface mode1 register 06 h 40 sil sil register 07 h 41 mod_2 interface mode2 register 08 h 42 mod_3 interface mode3 register 09 h 43 offx offset x 0a h 44 offy offset y 0b h 45 synch synchronicity 0c h 45 ifab ifab register 0d h 46 mod_4 interface mode4 register 0e h 47 tco_y temperature coefficient register 0f h 48 adc_x x-raw value 10 h 48 adc_y y-raw value 11 h 49 iif_cnt iif counter value 20 h 49
tle5012 specifications final data sheet 34 v 1.0, 2010-11 3.5.1.3.1 tle5 012 register status register stat offset reset value status register 00 h 8001 h field bits type description rd_st 15 r read status 0 b status values not changed since last readout 1 b status values changed reset: 1 b s_nr 14:13 w slave number is given at startup by the external circuit of ifa and ifb and can be changed via ssc-if reset: 00 b no_gmr_a 12 ru no valid gmr angle value cyclic check of dspu output. 0 b valid gmr angle value on the interface 1 b no valid gmr angle value on the interface (e.g test vectors) reset: 0 b no_gmr_xy 11 ru no valid gmr xy values cyclic check of adc input. 0 b valid gmr_xy values on the adc input 1 b no valid gmr_xy values on the adc input (e.g. test vectors) reset: 0 b s_rom 10 r status rom 1) check of rom-crc at startup. after fail dspu does not start. spi access possible. 0 b crc ok 1 b crc fail or running reset: 0 b 15 8 7 0 15 15 r rd_st 14 13 w s_nr 12 12 ru no_gmr_ a 11 11 ru no_gmr_ xy 10 10 r s_rom 9 9 ru s_adct 8 8 res 7 7 ru s_magol 6 6 ru s_xyol 5 5 ru s_ov 4 4 ru s_dspu 3 3 ru s_fuse 2 2 ru s_vr 1 1 ru s_wd 0 0 ru s_rst
tle5012 specifications final data sheet 35 v 1.0, 2010-11 s_adct 9 ru status adc-test 1) check of signal path with test vectors. all test vectors at startup tested. activation in operation via as_adct possible. 0 b test vectors ok 1 b test vectors out of limit reset: 0 b s_magol 7 ru status magnitude out of limit 1) cyclic check of available magnetic field strength. deactivation via as_vec_mag. 0 b gmr-magnitude ok 1 b gmr-magnitude out of limit reset: 0 b s_xyol 6 ru status x,y data out of limit 1) cylcic check of x and y raw values. deactivation via as_vec_xy 0 b x,y data ok 1 b x,y data out of limit (>23230 digits) reset: 0 b s_ov 5 ru status overflow 1) cyclic check of dspu overflow. deactivation via as_ov. 0 b no dspu overflow occurred 1 b dspu overflow occurred reset: 0 b s_dspu 4 ru status digital signal processing unit check of dspu, cordic and capcom at startup. activation in operation via as_dspu possible. 0 b dspu self-test ok 1 b dspu self-test not ok, or self-test is running reset: 0 b s_fuse 3 ru status fuse crc 1) cyclic crc check of laser-cut-fuses. deactivation via as_fuse and disabled by activated autocalibration. note: changing of fused parame ters results in new crc, which differs from stor ed crc --> fuse crc fail 0 b fuse crc ok 1 b fuse crc fail reset: 0 b s_vr 2 ru status voltage regulator 1) permanent check of internal and external supply voltages. deactivation via as_vr 0 b voltages ok 1 b v dd overvoltage; v dd undervoltage; v dd -off; gnd- off; or v ovg ; v ova ; v ovd too high reset: 0 b field bits type description
tle5012 specifications final data sheet 36 v 1.0, 2010-11 activation status register s_wd 1 ru status watchdog permanent check of watchdog. after overflow, a reset is necessary. deactivation via as_wd 0 b after chip reset 1 b watchdog counter expired (dspu stop), as_rst must be activated reset: 0 b s_rst 0 ru status reset permanent check of any reset. deactivation via as_rst. 0 b no reset since last readout 1 b indication of power-up, short power-break or active reset reset: 1 b 1) reset to ?0? after readout acstat offset reset value activation status register 01 h 5efe h field bits type description res 15:10 w reserved reset: 010111 b as_adct 9 w enable adc testvector check 0 b after execution 1 b activation of adc testvector check reset: 1 b as_vec_mag 7 w activation of magnitude check 0 b monitoring of magnitude disabled 1 b monitoring of magnitude enabled reset: 1 b field bits type description 15 8 7 0 15 10 w res 9 9 w as_adct 8 8 res 7 7 w as_vec_ mag 6 6 w as_vec_ xy 5 5 w as_ov 4 4 w as_dspu 3 3 w as_fuse 2 2 w as_vr 1 1 w as_wd 0 0 w as_rst
tle5012 specifications final data sheet 37 v 1.0, 2010-11 angle value register as_vec_xy 6 w activation of x,yout of limit check 0 b monitoring of x,y out of limit disabled 1 b monitoring of x,y out of limit enabled reset: 1 b as_ov 5 w enable of dspu overflow check 0 b monitoring of dspu overflow disabled 1 b monitoring of dspu overflow enabled reset: 1 b as_dspu 4 w activation dspu bist 0 b after execution 1 b activation of dspu bist or bist running reset: 1 b as_fuse 3 w activation fuse crc 0 b monitoring of fuse crc disabled 1 b monitoring of fuse crc enabled reset: 1 b as_vr 2 w enable voltage regulator check 0 b check of regulator voltages disabled 1 b check of regulator voltages enabled reset: 1 b as_wd 1 w enable dspu watchdog-hw-reset 0 b dspu watchdog monitoring disabled 1 b dspu watchdog monitoring enabled reset: 1 b as_rst 0 w activation of hardware reset activation occurs after csq sw itches from ?0? to ?1? after ssc transfer. 0 b after execution 1 b activation of hw reset reset: 0 b aval offset reset value angle value register 02 h 8000 h field bits type description 15 8 7 0 15 15 r rd_av 14 ru ang_val 7 0 ru ang_val
tle5012 specifications final data sheet 38 v 1.0, 2010-11 angle speed register field bits type description rd_av 15 r read status, angle value 0 b no new angle value since last readout 1 b new angle value (ang_val) present reset: 1 b ang_val 14:0 ru calculated angle value (ang_range = 0x080) (4) 4000 h -180 0000 h 0 3fff h +179.99 reset: 0 h aspd offset reset value angle speed register 03 h 8000 h field bits type description rd_as 15 r read status, angle speed 0 b no new angle speed value since last readout 1 b new angle speed value (ang_spd) present reset: 1 b ang_spd 14:0 ru calculated angle speed without prediction differenc e among three consecutive angle values. with prediction, difference among three predicted angle values. (5) reset: 0 h ] [ _ 2 360 ] [ 15 digits val ang angle = 15 8 7 0 15 15 r rd_as 14 ru ang_spd 7 0 ru ang_spd ] [ 2 ] [ _ 2 ] [ ] / [ 15 s t digits spd ang anglerange s speed upd q q
tle5012 specifications final data sheet 39 v 1.0, 2010-11 angle revolution register frame synchronization register arev offset reset value angle revolution register 04 h 8000 h field bits type description rd_rev 15 r read status, revolution 0 b no new values since last readout 1 b new value (revol) present reset: 1 b fcnt 14:9 wu frame counter (unsigned 6-bit value) counts every new angle value reset: 0 h revol 8:0 ru number of revolutions (signed 9-bit value) if prediction is enabled, revolution counter is one schedule delayed related to ang_val. reset: 0 h fsync offset reset value frame synchronization register 05 h 0000 h 15 8 7 0 15 15 r rd_rev 14 9 wu fcnt 8 ru revol 7 0 ru revol 15 8 7 0 15 9 wu fsync 8 res 7 0 res
tle5012 specifications final data sheet 40 v 1.0, 2010-11 interface mode1 register field bits type description fsync 15:9 wu frame synchronization counter value sub-counter within one frame. reset: 0 h mod_1 offset reset value interface mode1 register 06 h 8001 h field bits type description fir_md 15:14 w filter decimation setting (update rate setting) 00 b 21.3 s (only for raw x/y-values) 01 b 42.7 s 10 b 85.3 s 11 b 170.6 s reset: 10 b clk_sel 4 w clock source select in absence of external clock or pll out of lock, automatically switch to internal oscillator 0 b internal oscillator 1 b external 4-mhz clock reset: 0 b ssc_od 3 w ssc interface 0 b push-pull 1 b open drain (default within tle5012-e0318 and TLE5012-E0742) reset: 0 b 15 8 7 0 15 14 w fir_md 13 res 75 res 4 4 w clk_sel 3 3 w ssc_od 2 2 w dspu_ho ld 10 w iif_mod
tle5012 specifications final data sheet 41 v 1.0, 2010-11 sil register dspu_hold 2 w hold dspu operation if dspu is on hold, no wd reset is performed by dspu. deactivate watchdog with as_wd before setting dspu on hold. 0 b dspu in normal schedule operation 1 b dspu is on hold reset: 0 b iif_mod 1:0 w incremental interface mode 00 b iif disabled 01 b a/b operation with index on data 10 b step/direction operation with index on data 11 b not allowed reset: 01 b sil offset reset value sil register 07 h 0000 h field bits type description filt_par 15 w filter parallel 0 b filter parallel disabled 1 b filter parallel enabled (source: x-value) reset: 0 b filt_inv 14 w filter inverted 0 b filter inverted disabled 1 b filter inverted enabled reset: 0 b fuse_rel 10 w fuse reload 0 b fuse reload disabled 1 b fuse parameters reloaded to dspu at next cycle start reset: 0 b field bits type description 15 8 7 0 15 15 w filt_pa r 14 14 w filt_in v 13 11 res 10 10 w fuse_re l 9 res 7 7 res 6 6 w adctv_e n 53 w adctv_y 20 w adctv_x
tle5012 specifications final data sheet 42 v 1.0, 2010-11 interface mode2 register adctv_en 6 w adc-test vectors 0 b adc-test vectors disabled 1 b adc-test vectors enabled reset: 0 b adctv_y 5:3 w test vector y 000 b 0v 001 b +70% 010 b +100% 011 b +overflow 101 b -70% 110 b -100% 111 b -overflow reset: 0 h adctv_x 2:0 w test vector x 000 b 0v 001 b +70% 010 b +100% 011 b +ov 101 b -70% 110 b -100% 111 b -ov reset: 0 h mod_2 offset reset value interface mode2 register 08 h 0800 h field bits type description ang_range 14:4 w angle range angle range [] = 360 * (2 7 / ang_range[digits]) 200 h represents 90 080 h represents 360 reset: 080 h field bits type description 15 8 7 0 15 15 res 14 w ang_range 74 w ang_range 3 3 w ang_dir 2 2 w predict 10 w autocal
tle5012 specifications final data sheet 43 v 1.0, 2010-11 interface mode3 register ang_dir 3 w angle direction 0 b counterclockwise rotation of magnet 1 b clockwise rotation of magnet reset: 0 b predict 2 w prediction 0 b prediction disabled 1 b prediction enabled (default within tle5012-e0318 and TLE5012-E0742) reset: 0 b autocal 1:0 w autocalibration mode autocalibration modes are described on page 23 . 00 b no autocalibration 01 b autocalibration mode 1 (default within tle5012- e0318 and TLE5012-E0742) 10 b autocalibration mode 2 11 b autocalibration mode 3 reset: 00 b mod_3 offset reset value interface mode3 register 09 h 0000 h field bits type description ang_base 15:4 w angle base 800 h -180 000 h 0 001 h 0.0879 7ff h +179.912 reset: 000 h spikef 3 w analog spike filters of input pads 0 b spike filter disabled 1 b spike filter enabled reset: 0 b field bits type description 15 8 7 0 15 w ang_base 74 w ang_base 3 3 w spikef 2 2 res 10 w pad_drv
tle5012 specifications final data sheet 44 v 1.0, 2010-11 offset x register pad_drv 1:0 w configuration of pad-driver 00 b ifa/ifb: strong driver, data: strong driver, fast edge 01 b ifa/ifb: strong driver, data: strong driver, slow edge 10 b ifa/ifb: weak driver, data: medium driver, fast edge (default within tle5012-e0318 and TLE5012-E0742) 11 b ifa/ifb: weak driver, data: weak driver, slow edge reset: 00 b offx offset reset value offset x 0a h 0000 h field bits type description x_offset 15:4 w offset correction of x-value in digits reset: 0 h field bits type description 15 8 7 0 15 w x_offset 74 w x_offset 30 res
tle5012 specifications final data sheet 45 v 1.0, 2010-11 offset y register synchronicity register offy offset reset value offset y 0b h 0000 h field bits type description y_offset 15:4 w offset correction of y-value in digits reset: 0 h synch offset reset value synchronicity 0c h 0000 h field bits type description synch 15:4 w amplitude synchronicity +2047 d 112.494% 0 d 100% -2048 d 87.500% reset: 0 h 15 8 7 0 15 w y_offset 74 w y_offset 30 res 15 8 7 0 15 w synch 74 w synch 30 res
tle5012 specifications final data sheet 46 v 1.0, 2010-11 ifab register ifab offset reset value ifab register 0d h 0003 h field bits type description ortho 15:4 w orthogonality correction of x and y components +2047 d 11.2445 0 d 0 -2048 d -11.2500 reset: 0 h ifab_od 2 w ifa & ifb open drain 0 b push-pull 1 b open drain (default within tle5012-e0318 and TLE5012-E0742) reset: 0 b ifab_hyst 1:0 w hsm hysteresis 00 b 0 01 b 0.09 10 b 0.27 11 b 0.625 reset: 11 b 15 8 7 0 15 w ortho 74 w ortho 3 3 res 2 2 w ifab_od 10 w ifab_hyst
tle5012 specifications final data sheet 47 v 1.0, 2010-11 interface mode4 register mod_4 offset reset value interface mode4 register 0e h 0000 h field bits type description tco_x_t 15:9 w offset temperature coefficient for x-component reset: 0 h hsm_plp 7:5 w hall switch mode; pole pair configuration 000 b 2 pole pairs 001 b 3 pole pairs (default within tle5012-e0318) 010 b 4 pole pairs 011 b 6 pole pairs 100 b 7 pole pairs (default within TLE5012-E0742) 101 b 8 pole pairs 110 b 12 pole pairs 111 b 16 pole pairs reset: 000 b ifab_res 4:3 w ifab resolution 00 b 12 bit = 0.088 (244hz) 01 b 11 bit = 0.176 (488hz) 10 b 10 bit = 0.352 (977hz) 11 b 9 bit = 0.703 (1953hz) reset: 00 b 15 8 7 0 15 9 w tco_x_t 8 8 res 75 w hsm_plp 43 w ifab_res 20 w if_md
tle5012 specifications final data sheet 48 v 1.0, 2010-11 temperature coefficient register x-raw value register if_md 2:0 w interface mode selected by external circuit of clk pin at power-on time. clk pin connected to v dd --> incremental interface is selected; clk pin connected to gnd --> if_md stored interface is used. switching to another interfac e during operation needs to stop the dspu (dspu_hold). note: combinations not listed below are not allowed 000 b ssc mode; iif 001 b ssc mode; pwm 010 b ssc mode; hsm (default within tle5012-e0318 and TLE5012-E0742) reset: 000 b tco_y offset reset value temperature coefficient register 0f h 0000 h field bits type description tco_y_t 15:9 w offset temperature coefficient for y-component reset: 0 h crc_par 7:0 w crc of parameters crc of parameters from address 08 h to 0f h . when changing any settings within these registers, this crc has to be updated. reset: 0 h adc_x offset reset value x-raw value 10 h 0000 h field bits type description 15 0 15 9 w tco_y_t 8 8 res 70 w crc_par
tle5012 specifications final data sheet 49 v 1.0, 2010-11 y-raw value register increment counter register field bits type description adc_x 15:0 r adc value of x-gmr read out of this regi ster will update adc_y reset: 0 h adc_y offset reset value y-raw value 11 h 0000 h field bits type description adc_y 15:0 r adc value of y-gmr updated when adc_x or adc_y is read. reset: 0 h iif_cnt offset reset value iif counter value 20 h 0000 h 15 0 15 0 r adc_x 15 0 15 0 r adc_y 15 0 15 12 res 11 0 r iif_cnt
tle5012 specifications final data sheet 50 v 1.0, 2010-11 3.5.1.4 communication examples this section gives some short spi communication exampl es. the sensor has to be selected first via csq, and sck must be available for the communication. field bits type description iif_cnt 11:0 r counter value of increments this value can be used for synchronization purposes between sensor and counter value on microcontroller side. reset: 0 h table 19 ssc command to read the angle value ssc word no. description master transmitting tle5012 transmitting note 1 command 1_0000_0_000010_0001 2 read data 1_xxxxxxxxxxxxxxx read angle value 3 safety word 1_1_1_1_xxxx_xxxxxxxx read safety word table 20 ssc command to read angle speed and angle revolution ssc word no. description master transmitting tle5012 transmitting note 1 command 1_0000_0_000011_0010 2 read data 1_xxxxxxxxxxxxxxx read angle speed 3 read data 1_xxxxxx_xxxxxxxxx read angle revolution 4 safety word 1_1_1_1_xxxx_xxxxxxxx read safety word table 21 ssc command to change interface mode2 register ssc word no. description master transmitting tle5012 transmitting note 1 command 0_1010_0_001000_0001 2 write data 0_00010000000_1_0_01 ang_range: 080 h ; ang_dir: 1 b ; predict: 0 b ; autocal: 01 b 3 safety word 1_1_1_1_xxxx_xxxxxxxx read safety word
tle5012 specifications final data sheet 51 v 1.0, 2010-11 3.5.2 pulse-width modulation interface the pulse-width modulation (pwm) interface can be selected via spi. the pwm update rate can be changed within the register 0e h (ifab_res) in following steps: ? 0.25 khz with 12-bit resolution ? 0.5 khz with 12-bit resolution ? 1.0 khz with 12-bit resolution ? 2.0 khz with 12-bit resolution pwm uses a square wave with constant frequency whose duty cycle is modula ted, resulting in an average value of the waveform. figure 22 shows the principal behavior of a pwm with various du ty cycles and the definition of timing values. the duty cycle of a pwm is defined by following general formulas: (6) the range between 0 - 6.25% and 93.75 - 100% is used on ly for diagnostic purposes. more details are given in table 22 . figure 22 typical example for a pwm signal table 22 pwm interface parameter symbol values unit note / test condition min. typ. max. pwm output frequency f pwm 244 - 1953 hz selectable by ifab_res 1)2) pwm pwm off on pwm pwm on t f t t t t t cycle duty 1 = + = = t on ?0' t on = high level off = low level duty cycle = 5% duty cycle = 50% duty cycle = 95% t pwm t off vdd u ifa vdd u ifa t ?0' t vdd u ifa ?0'
tle5012 specifications final data sheet 52 v 1.0, 2010-11 output duty cycle range dy pwm 6.25 - 93.75 % absolute angle 2) - 2 - % electrical error (s_rst; s_vr) 2) - 98 - % system error (s_fuse; s_ov; s_xyol; s_magol; s_adct) 2) 0 - 1 % short to gnd 2) 99 - 100 % short to v dd , power-loss 2) pwm period variation t pwmvar -5 - 5 % 2)3) 1) f pwm = (f dig * 2 ifab_res ) / (24 * 4096) 2) not subject to production test - ve rified by design/characterization 3) depends on internal oscillator frequency variation ( section 3.4.6 ) table 22 pwm interface parameter symbol values unit note / test condition min. typ. max.
tle5012 specifications final data sheet 53 v 1.0, 2010-11 3.5.3 hall switch mode the hall switch mode (hsm) within th e tle5012 makes it possible to emulat e the output of three hall switches. hall switches are often used in electrical commutated moto rs to get information about the rotor position. with these three output signals, the motor will be commutated in the right wa y. depending on which pol e pairs of the rotor are used, various electrical periods have to be utilized. this is selectable within 0e h (hsm_plp). within the tle5012- e0318 three pole pairs are fused; within the TLE5012-E0742, seven pole pairs are fused. figure 23 depicts the three output signals with the relationsh ip between electrical angle and mech anical angle. the mechanical 0 point is always used as a reference. the hsm is generally used with open-drain output, but it can be changed to push-pull within ssc_od and ifab_od. figure 23 hall switch mode the hsm interface can be selected by connecting clk to gnd, and csq has to be logic ?1?. table 23 hall switch mode parameter symbol values unit note / test condition min. typ. max. rotation speed n - - 10000 rpm 2) hs1 hs2 hs3 0 electrical angle 60 120 180 240 300 360 hall-switch-mode: 3phase generation angle mech. angle with 8 pole pairs 0 7.5 15 22.5 30 37.5 45 0 20 40 60 80 100 120 mech. angle with 3 pole pairs
tle5012 specifications final data sheet 54 v 1.0, 2010-11 to avoid toggling on the hs outputs during mechanical vibration of the rotor, hysteresis (ifab_hyst) is recommended ( figure 24 ). electrical angle accuracy elect - 1.2 2 2 pole pairs with autocalibration 1)2) - 1.8 3 3 pole pairs with autocal. 1)2) - 2.4 4 4 pole pairs with autocal. 1)2) - 3.6 6 6 pole pairs with autocal. 1)2) - 4.2 7 7 pole pairs with autocal. 1)2) - 4.8 8 8 pole pairs with autocal. 1)2) - 7.2 12 12 pole pairs with autocal. 1)2) - 9.6 16 16 pole pairs with autocal. 1)2) mechanical angle switching hysteresis hshystm 0 - 0.625 selectable by ifab_hyst 2)3)4) electrical angle switching hysteresis 5) hshystel - 1.25 - 2 pole pairs; ifab_hyst=11 1)2) - 1.88 - 3 pole pairs; ifab_hyst=11 1)2) - 2.50 - 4 pole pairs; ifab_hyst=11 1)2) - 3.75 - 6 pole pairs; ifab_hyst=11 1)2) - 4.38 - 7 pole pairs; ifab_hyst=11 1)2) - 5.00 - 8 pole pairs; ifab_hyst=11 1)2) - 7.50 - 12 pole pairs; ifab_hyst=11 1)2) - 10 - 16 pole pairs; ifab_hyst=11 1)2) fall time t hsfall -0.021 sr l = 2.2 k ? ; c l < 50 pf 2) rise time t hsrise -0.41 sr l = 2.2 k ? ; c l < 50 pf 2) 1) depends on internal oscillator frequency variation ( section 3.4.6 ) 2) not subject to production test - ve rified by design/characterization 3) gmr hysteresis not considered 4) minimum hysteresis without switching 5) the hysteresis has to be considered only when rotation direction is changed. table 23 hall switch mode parameter symbol values unit note / test condition min. typ. max.
tle5012 specifications final data sheet 55 v 1.0, 2010-11 figure 24 hs hysteresis 3.5.4 incremental interface the incremental interface (iif) uses an up/down counte r of a microcontroller for the angle transmission. the synchronization is done by the parallel active ssc interf ace. the angle value read out by the ssc interface can be compared to the stored counter value. in case of a non-synchronization, the microcontroller adds the difference to the actual counter value to synchronize the tle5012 wit h the microcontroller. the resolution of the iif can be selected within the interface mode4 register (mod_4) under ifab_res. after startup, the iif pulses out the actual absolute angle value to notify the microcontroller about the absolute position. in register mod_1 the iif can be set in a/b mode or step/direction mode (iif_mod). a/b mode the phase shift between phase a and b indicates a clockw ise (a follows b) or a co unterclockwise (b follows a) rotation of the magnet. step/direction mode phase a pulses out the increments and phase b indicates the direction ( figure 25 ). figure 25 incremental interface with step/direction mode ideal switching point elect hshystel hshystel elect 0 0 1 2 3 4 3 2 1 step direction counter value incremental interface (st ep/ d ir m ode) v h v l v h v l
tle5012 specifications final data sheet 56 v 1.0, 2010-11 figure 26 incremental interface protocol wi th symbolic illustration of spi interface index signal the index signal is generated via the data pin while csq is high (no ssc communication). the index signal is coded in quadrants via a pwm sequence, figure 27 . figure 27 iif index coding table 24 incremental interface parameter symbol values unit note / test condition min. typ. max. incremental output frequency f inc - - 1.0 mhz frequency of phase a and phase b 1) 0 1 2 3 4 3 2 1 phase a counter value d0 d1 d2 d3 d11 d13 d14 d1 5 data sck csq phase b c 12bit up/down counter ifa ifb a b igmr- sensor n s vdd data sck gnd ssc ssc inc csq spi interface incremental interface (a/b mode) v h v l v h v l 90 el. phase shift 0 90 180 270 0 t 0 t 90 t 180 t 270 index angle
tle5012 specifications final data sheet 57 v 1.0, 2010-11 3.6 test structure 3.6.1 adc test vectors it is possible to feed the adcs wit h appropriate values to simulate a certain magnet position and other gmr effects. this test can be activated within the sil register (adctv_en). with adctv_y and adctv_x the vector length can be adjusted as shown in figure 28 . the values are generated with resistors on the chip. the following x/y adc values can be programmed: ? 4 points, circle amplitude = 70% (0,90, 180, 270) ? 8 points, circle amplitude = 100% (0, 45, 90, 135, 180, 225, 270, 315) ? 8 points, circle amplitude = 122.1% (35.3, 54.7, 125.3, 144.7, 215.3, 234.7, 305.3, 324.7) ? 4 points, circle amplitude = 141.4% (45, 135, 225, 315) note: the 100% values typically correspond to 21700 digits and the 70% values to 15500 digits. index t 0 -5- s0 1) t 90 -10- s90 1) t 180 - 15 - s 180 1) t 270 - 20 - s 270 1) 1) not subject to production test - ve rified by design/characterization table 25 adc test vectors register bits x/y values (decimal) min. typ. max. 000 0 001 15500 010 21700 011 32767 100 1) 1) invalid 0 101 -15500 110 -21700 111 -32768 table 24 incremental interface (cont?d) parameter symbol values unit note / test condition min. typ. max.
tle5012 specifications final data sheet 58 v 1.0, 2010-11 figure 28 adc test vectors examples for adc te st vector check the sensor has to be selected first via csq and sck must be availabl e for the communication. table 26 shows the structure of the communication to en able the adc test vector for 54.7. table 26 ssc command to enab le adc test vector check ssc word no. description master transmitting tle5012 transmitting note 1 command 0_1010_0_000111_0001 2 write data 0_0_000_0_000_1_010_001 check of 54.7 3 safety word 1_1_1_0_xxxx_xxxxxxxx table 27 structure of write data for some different test vectors ssc word no. description master transmitting tle5012 transmitting note 1 write data 0_0_000_0_000_1_001_101 ~135 2 write data 0_0_000_0_000_1_010_110 ~135 3 write data 0_0_000_0_000_1_101_110 ~215.3 4 write data 0_0_000_0_000_1_101_000 ~270 5 write data 0_0_000_0_000_1_101_010 ~324.7 adctv_x adctv_y 0% 122.1% 100 .0% 70% 141.4%
tle5012 specifications final data sheet 59 v 1.0, 2010-11 3.7 overvoltage comparators various comparators monitor the voltage in order to ensur e error-free operation. the overvoltage must be active at least 256 periods of t dig to set the test comparator bits in the ssc in terface registers. this serves as digital spike suppression. 3.7.1 internal supply voltage comparators every voltage regulator has an overvoltage (ov) comparator to detect a malfunction. if the nominal output voltage of 2.5 v is larger than v ovg , v ova and v ovd , then this overvoltage comparator is activated. figure 29 ov comparator 3.7.2 v dd overvoltage detection the overvoltage detection comparator monitors the external supply voltage at the v dd pin. it activates the s_vr bit ( figure 29 ). 3.7.3 gnd - off comparator the gnd - off comparator is used to detect a voltage di fference between the gnd pin and sck. it activates the s_vr bit of the ssc interface. this circuit can detect a disconnection of the supply gnd pin. table 28 test comparators parameter symbol values unit note / test condition min. typ. max. overvoltage detection v ovg -2.80- v v ova -2.80- v v ovd -2.80- v v dd overvoltage v ddov -6.05- v v dd undervoltage v dduv -2.70- v gnd - off voltage v gndoff - -0.55 - v v dd - off voltage v vddoff -0.55- v spike filter delay t del -10- s 1) 1) not subject to production test - ve rified by design/characterization ref - + 10s spike filter xxx_ov v dda gnd gnd v dd v rg v ra v rd
tle5012 specifications final data sheet 60 v 1.0, 2010-11 figure 30 gnd - off comparator 3.7.4 v dd - off comparator the v dd - off comparator detects a disconnection of the vd d pin supply voltage. in this case, the tle5012 is supplied by the sck and csq input pins via th e esd structures. it activates the s_vr bit. figure 31 v dd - off comparator - + 10s spike filter gnd_off v dda gnd sck gnd v dd +dv diode- reference 1s mono flop 10s spike filter vdd _off v dda gnd v dd csq sck -dv gnd 1s mono flop - + v vddoff
tle5012 package information final data sheet 61 v 1.0, 2010-11 4 package information 4.1 package parameters 4.2 package outline figure 32 pg-dso-8 package dimensions table 29 package parameters parameter symbol limit values unit notes min. typ. max. thermal resistance r thja - 150 200 k/w junction to air 1) 1) according to jedec jesd51-7 r thjc - - 75 k/w junction to case r thjl - - 85 k/w junction to lead soldering moisture level msl 3 260c lead frame cu plating sn 100% > 7 m
tle5012 package information final data sheet 62 v 1.0, 2010-11 figure 33 position of sensing element 4.3 footprint figure 34 footprint of pg-dso-8 4.4 packing figure 35 tape and reel 0.65 1.31 5.69 1.27 8 6.4 5.2 0.3 0.3 12 2.1 1.75
tle5012 package information final data sheet 63 v 1.0, 2010-11 4.5 marking processing note: for processing recommendations, please refer to infineon?s notes on processing position marking description 1st line 5012xx see ordering table on page 8 2nd line xxx lot code 3rd line gxxxx g..green, 4-digit..date code
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